-static int __attribute__((warn_unused_result))
-probe_cpu(void)
-{
- unsigned int eax, ebx, ecx, edx, max_level;
- unsigned int fms, family, model;
-
- /* CPUID(0):
- * - EAX: Maximum Input Value for Basic CPUID Information
- * - EBX: "Genu" (0x756e6547)
- * - EDX: "ineI" (0x49656e69)
- * - ECX: "ntel" (0x6c65746e)
- */
- max_level = ebx = ecx = edx = 0;
- __get_cpuid(0, &max_level, &ebx, &ecx, &edx);
- if (ebx != 0x756e6547 && edx != 0x49656e69 && ecx != 0x6c65746e) {
- ERROR("turbostat plugin: Unsupported CPU (not Intel)");
- return -1;
- }
-
- /* CPUID(1):
- * - EAX: Version Information: Type, Family, Model, and Stepping ID
- * + 4-7: Model ID
- * + 8-11: Family ID
- * + 12-13: Processor type
- * + 16-19: Extended Model ID
- * + 20-27: Extended Family ID
- * - EDX: Feature Information:
- * + 5: Support for MSR read/write operations
- */
- fms = ebx = ecx = edx = 0;
- __get_cpuid(1, &fms, &ebx, &ecx, &edx);
- family = (fms >> 8) & 0xf;
- model = (fms >> 4) & 0xf;
- if (family == 0xf)
- family += (fms >> 20) & 0xf;
- if (family == 6 || family == 0xf)
- model += ((fms >> 16) & 0xf) << 4;
- if (!(edx & (1 << 5))) {
- ERROR("turbostat plugin: Unsupported CPU (no MSR support)");
- return -1;
- }
-
- /*
- * CPUID(6):
- * - EAX:
- * + 0: Digital temperature sensor is supported if set
- * + 6: Package thermal management is supported if set
- * - ECX:
- * + 0: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF).
- * + 3: The processor supports performance-energy bias preference if set.
- * It also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS
- *
- * This check is valid for both Intel and AMD
- */
- eax = ebx = ecx = edx = 0;
- __get_cpuid(0x6, &eax, &ebx, &ecx, &edx);
- do_dts = eax & (1 << 0);
- do_ptm = eax & (1 << 6);
- if (!(ecx & (1 << 0))) {
- ERROR("turbostat plugin: Unsupported CPU (No APERF)");
- return -1;
- }
-
- /*
- * Enable or disable C states depending on the model and family
- */
- if (family == 6) {
- switch (model) {
- /* Atom (partial) */
- case 0x27:
- do_smi = 0;
- do_core_cstate = 0;
- do_pkg_cstate = (1 << 2) | (1 << 4) | (1 << 6);
- break;
- /* Silvermont */
- case 0x37: /* BYT */
- case 0x4D: /* AVN */
- do_smi = 1;
- do_core_cstate = (1 << 1) | (1 << 6);
- do_pkg_cstate = (1 << 6);
- break;
- /* Nehalem */
- case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
- case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
- case 0x1F: /* Core i7 and i5 Processor - Nehalem */
- case 0x2E: /* Nehalem-EX Xeon - Beckton */
- do_smi = 1;
- do_core_cstate = (1 << 3) | (1 << 6);
- do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
- break;
- /* Westmere */
- case 0x25: /* Westmere Client - Clarkdale, Arrandale */
- case 0x2C: /* Westmere EP - Gulftown */
- case 0x2F: /* Westmere-EX Xeon - Eagleton */
- do_smi = 1;
- do_core_cstate = (1 << 3) | (1 << 6);
- do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
- break;
- /* Sandy Bridge */
- case 0x2A: /* SNB */
- case 0x2D: /* SNB Xeon */
- do_smi = 1;
- do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
- do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
- break;
- /* Ivy Bridge */
- case 0x3A: /* IVB */
- case 0x3E: /* IVB Xeon */
- do_smi = 1;
- do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
- do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
- break;
- /* Haswell Bridge */
- case 0x3C: /* HSW */
- case 0x3F: /* HSW */
- case 0x46: /* HSW */
- do_smi = 1;
- do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
- do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
- break;
- case 0x45: /* HSW */
- do_smi = 1;
- do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
- do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10);
- break;
- /* Broadwel */
- case 0x4F: /* BDW */
- case 0x56: /* BDX-DE */
- do_smi = 1;
- do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
- do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
- break;
- case 0x3D: /* BDW */
- do_smi = 1;
- do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
- do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10);
- break;
- default:
- do_smi = 0;
- do_core_cstate = 0;
- do_pkg_cstate = 0;
- break;
- }
- switch (model) {
- case 0x2A: /* SNB */
- case 0x3A: /* IVB */
- case 0x3C: /* HSW */
- case 0x45: /* HSW */
- case 0x46: /* HSW */
- case 0x3D: /* BDW */
- do_rapl = RAPL_PKG | RAPL_CORES | RAPL_GFX;
- break;
- case 0x3F: /* HSX */
- case 0x4F: /* BDX */
- case 0x56: /* BDX-DE */
- do_rapl = RAPL_PKG | RAPL_DRAM ;
- break;
- case 0x2D: /* SNB Xeon */
- case 0x3E: /* IVB Xeon */
- do_rapl = RAPL_PKG | RAPL_CORES | RAPL_DRAM;
- break;
- case 0x37: /* BYT */
- case 0x4D: /* AVN */
- do_rapl = RAPL_PKG | RAPL_CORES;
- break;
- default:
- do_rapl = 0;
- }
- } else {
- ERROR("turbostat plugin: Unsupported CPU (family: %#x, "
- "model: %#x)", family, model);
- return -1;
- }
-
- /* Override detected values with configuration */
- if (apply_config_core_cstate)
- do_core_cstate = config_core_cstate;
- if (apply_config_pkg_cstate)
- do_pkg_cstate = config_pkg_cstate;
- if (apply_config_smi)
- do_smi = config_smi;
- if (apply_config_dts)
- do_dts = config_dts;
- if (apply_config_ptm)
- do_ptm = config_ptm;
- if (apply_config_rapl)
- do_rapl = config_rapl;
-
- if (do_rapl) {
- unsigned long long msr;
- if (get_msr(0, MSR_RAPL_POWER_UNIT, &msr))
- return 0;
-
- if (model == 0x37)
- rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
- else
- rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
- }
-
- return 0;
+static int __attribute__((warn_unused_result)) probe_cpu(void) {
+ unsigned int eax, ebx, ecx, edx, max_level;
+ unsigned int fms, family, model;
+
+ /* CPUID(0):
+ * - EAX: Maximum Input Value for Basic CPUID Information
+ * - EBX: "Genu" (0x756e6547)
+ * - EDX: "ineI" (0x49656e69)
+ * - ECX: "ntel" (0x6c65746e)
+ */
+ max_level = ebx = ecx = edx = 0;
+ __get_cpuid(0, &max_level, &ebx, &ecx, &edx);
+ if (ebx != 0x756e6547 && edx != 0x49656e69 && ecx != 0x6c65746e) {
+ ERROR("turbostat plugin: Unsupported CPU (not Intel)");
+ return -1;
+ }
+
+ /* CPUID(1):
+ * - EAX: Version Information: Type, Family, Model, and Stepping ID
+ * + 4-7: Model ID
+ * + 8-11: Family ID
+ * + 12-13: Processor type
+ * + 16-19: Extended Model ID
+ * + 20-27: Extended Family ID
+ * - EDX: Feature Information:
+ * + 5: Support for MSR read/write operations
+ */
+ fms = ebx = ecx = edx = 0;
+ __get_cpuid(1, &fms, &ebx, &ecx, &edx);
+ family = (fms >> 8) & 0xf;
+ model = (fms >> 4) & 0xf;
+ if (family == 0xf)
+ family += (fms >> 20) & 0xf;
+ if (family == 6 || family == 0xf)
+ model += ((fms >> 16) & 0xf) << 4;
+ if (!(edx & (1 << 5))) {
+ ERROR("turbostat plugin: Unsupported CPU (no MSR support)");
+ return -1;
+ }
+
+ /*
+ * CPUID(6):
+ * - EAX:
+ * + 0: Digital temperature sensor is supported if set
+ * + 6: Package thermal management is supported if set
+ * - ECX:
+ * + 0: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and
+ * IA32_APERF).
+ * + 3: The processor supports performance-energy bias preference if set.
+ * It also implies the presence of a new architectural MSR called
+ * IA32_ENERGY_PERF_BIAS
+ *
+ * This check is valid for both Intel and AMD
+ */
+ eax = ebx = ecx = edx = 0;
+ __get_cpuid(0x6, &eax, &ebx, &ecx, &edx);
+ do_dts = eax & (1 << 0);
+ do_ptm = eax & (1 << 6);
+ if (!(ecx & (1 << 0))) {
+ ERROR("turbostat plugin: Unsupported CPU (No APERF)");
+ return -1;
+ }
+
+ /*
+ * Enable or disable C states depending on the model and family
+ */
+ if (family == 6) {
+ switch (model) {
+ /* Atom (partial) */
+ case 0x27:
+ do_smi = 0;
+ do_core_cstate = 0;
+ do_pkg_cstate = (1 << 2) | (1 << 4) | (1 << 6);
+ break;
+ /* Silvermont */
+ case 0x37: /* BYT */
+ case 0x4D: /* AVN */
+ do_smi = 1;
+ do_core_cstate = (1 << 1) | (1 << 6);
+ do_pkg_cstate = (1 << 6);
+ break;
+ /* Nehalem */
+ case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
+ case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper
+ Forest */
+ case 0x1F: /* Core i7 and i5 Processor - Nehalem */
+ case 0x2E: /* Nehalem-EX Xeon - Beckton */
+ do_smi = 1;
+ do_core_cstate = (1 << 3) | (1 << 6);
+ do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ /* Westmere */
+ case 0x25: /* Westmere Client - Clarkdale, Arrandale */
+ case 0x2C: /* Westmere EP - Gulftown */
+ case 0x2F: /* Westmere-EX Xeon - Eagleton */
+ do_smi = 1;
+ do_core_cstate = (1 << 3) | (1 << 6);
+ do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ /* Sandy Bridge */
+ case 0x2A: /* SNB */
+ case 0x2D: /* SNB Xeon */
+ do_smi = 1;
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ /* Ivy Bridge */
+ case 0x3A: /* IVB */
+ case 0x3E: /* IVB Xeon */
+ do_smi = 1;
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ /* Haswell Bridge */
+ case 0x3C: /* HSW */
+ case 0x3F: /* HSW */
+ case 0x46: /* HSW */
+ do_smi = 1;
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ case 0x45: /* HSW */
+ do_smi = 1;
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) |
+ (1 << 9) | (1 << 10);
+ break;
+ /* Broadwel */
+ case 0x4F: /* BDW */
+ case 0x56: /* BDX-DE */
+ do_smi = 1;
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ case 0x3D: /* BDW */
+ do_smi = 1;
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) |
+ (1 << 9) | (1 << 10);
+ break;
+ default:
+ do_smi = 0;
+ do_core_cstate = 0;
+ do_pkg_cstate = 0;
+ break;
+ }
+ switch (model) {
+ case 0x2A: /* SNB */
+ case 0x3A: /* IVB */
+ case 0x3C: /* HSW */
+ case 0x45: /* HSW */
+ case 0x46: /* HSW */
+ case 0x3D: /* BDW */
+ do_rapl = RAPL_PKG | RAPL_CORES | RAPL_GFX;
+ break;
+ case 0x3F: /* HSX */
+ case 0x4F: /* BDX */
+ case 0x56: /* BDX-DE */
+ do_rapl = RAPL_PKG | RAPL_DRAM;
+ break;
+ case 0x2D: /* SNB Xeon */
+ case 0x3E: /* IVB Xeon */
+ do_rapl = RAPL_PKG | RAPL_CORES | RAPL_DRAM;
+ break;
+ case 0x37: /* BYT */
+ case 0x4D: /* AVN */
+ do_rapl = RAPL_PKG | RAPL_CORES;
+ break;
+ default:
+ do_rapl = 0;
+ }
+ } else {
+ ERROR("turbostat plugin: Unsupported CPU (family: %#x, "
+ "model: %#x)",
+ family, model);
+ return -1;
+ }
+
+ /* Override detected values with configuration */
+ if (apply_config_core_cstate)
+ do_core_cstate = config_core_cstate;
+ if (apply_config_pkg_cstate)
+ do_pkg_cstate = config_pkg_cstate;
+ if (apply_config_smi)
+ do_smi = config_smi;
+ if (apply_config_dts)
+ do_dts = config_dts;
+ if (apply_config_ptm)
+ do_ptm = config_ptm;
+ if (apply_config_rapl)
+ do_rapl = config_rapl;
+
+ if (do_rapl) {
+ unsigned long long msr;
+ if (get_msr(0, MSR_RAPL_POWER_UNIT, &msr))
+ return 0;
+
+ if (model == 0x37)
+ rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
+ else
+ rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
+ }
+
+ return 0;