static unsigned int do_snb_cstates;
static unsigned int do_c8_c9_c10;
static unsigned int do_slm_cstates;
-static unsigned int has_aperf;
-static unsigned int has_epb;
static unsigned int genuine_intel;
-static unsigned int has_invariant_tsc;
static unsigned int do_nehalem_platform_info;
static int do_smi;
static unsigned int do_rapl;
t->tsc = rdtsc(); /* we are running on local CPU of interest */
- if (has_aperf) {
- if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
- return -ERR_MSR_IA32_APERF;
- if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
- return -ERR_MSR_IA32_MPERF;
- }
+ if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
+ return -ERR_MSR_IA32_APERF;
+ if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
+ return -ERR_MSR_IA32_MPERF;
if (do_smi) {
if (get_msr(cpu, MSR_SMI_COUNT, &msr))
}
/* GHz */
- if (has_aperf && ((!aperf_mperf_unstable) || (!(t->aperf > t->tsc || t->mperf > t->tsc))))
+ if ((!aperf_mperf_unstable) || (!(t->aperf > t->tsc || t->mperf > t->tsc)))
turbostat_submit(NULL, "frequency", name, 1.0 * t->tsc / 1000000000 * t->aperf / t->mperf / interval_float);
/* SMI */
* this check is valid for both Intel and AMD
*/
__get_cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
- has_invariant_tsc = edx & (1 << 8);
-
- if (!has_invariant_tsc) {
+ if (!(edx & (1 << 8))) {
ERROR("No invariant TSC");
return -ERR_NO_INVARIANT_TSC;
}
*/
__get_cpuid(0x6, &eax, &ebx, &ecx, &edx);
- has_aperf = ecx & (1 << 0);
do_dts = eax & (1 << 0);
do_ptm = eax & (1 << 6);
- has_epb = ecx & (1 << 3);
-
- if (!has_aperf) {
+ if (!(ecx & (1 << 0))) {
ERROR("No APERF");
return -ERR_NO_APERF;
}
- do_nehalem_platform_info = genuine_intel && has_invariant_tsc;
+ do_nehalem_platform_info = genuine_intel;
do_nhm_cstates = genuine_intel; /* all Intel w/ non-stop TSC have NHM counters */
do_smi = do_nhm_cstates;
do_snb_cstates = is_snb(family, model);