Turbostat: SNB & later support MSR_PKG_C2_RESIDENCY

[collectd.git] / src / turbostat.c

diff --git a/src/turbostat.c b/src/turbostat.c
index 41b95e2..d62b522 100644 (file)
--- a/src/turbostat.c
+++ b/src/turbostat.c
@@ -61,17 +61,57 @@
 #define PLUGIN_NAME "turbostat"
 
 /*
+ * This tool uses the Model-Specific Registers (MSRs) present on Intel processors.
+ * The general description each of these registers, depending on the architecture,
+ * can be found in the Intel® 64 and IA-32 Architectures Software Developer Manual,
+ * Volume 3 Chapter 35.
+ */
+
+/*
  * If set, aperf_mperf_unstable disables a/mperf based stats.
  * This includes: C0 & C1 states, frequency
  *
- * This value is automatically set if mperf or aperf decreases
+ * This value is automatically set if mperf or aperf go backward
  */
 static _Bool aperf_mperf_unstable;
 
+/*
+ * Bitmask of the list of core C states supported by the processor.
+ * Currently supported C-states (by this plugin): 3, 6, 7
+ */
 static unsigned int do_core_cstate;
+
+/*
+ * Bitmask of the list of pacages C states supported by the processor.
+ * Currently supported C-states (by this plugin): 2, 3, 6, 7, 8, 9, 10
+ */
 static unsigned int do_pkg_cstate;
+
+/*
+ * Boolean indicating if the processor supports 'Digital temperature sensor'
+ * This feature enables the monitoring of the temperature of each core
+ *
+ * This feature has two limitations:
+ *  - if MSR_IA32_TEMPERATURE_TARGET is not supported, the absolute temperature might be wrong
+ *  - Temperatures above the tcc_activation_temp are not recorded
+ */
 static _Bool do_dts;
+
+/*
+ * Boolean indicating if the processor supports 'Package thermal management'
+ * This feature allows the monitoring of the temperature of each package
+ *
+ * This feature has two limitations:
+ *  - if MSR_IA32_TEMPERATURE_TARGET is not supported, the absolute temperature might be wrong
+ *  - Temperatures above the tcc_activation_temp are not recorded
+ */
 static _Bool do_ptm;
+
+/*
+ * Thermal Control Circuit Activation Temperature as configured by the user.
+ * This override the automated detection via MSR_IA32_TEMPERATURE_TARGET
+ * and should only be used if the automated detection fails.
+ */
 static unsigned int tcc_activation_temp;
 
 static unsigned int do_rapl;
@@ -258,6 +298,10 @@ for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_dat
        return 0;
 }
 
+/*
+ * Open a MSR device for reading
+ * Can change the scheduling affinity of the current process if multiple_read is 1
+ */
 static int __attribute__((warn_unused_result))
 open_msr(int cpu, _Bool multiple_read)
 {
@@ -287,6 +331,9 @@ open_msr(int cpu, _Bool multiple_read)
        return fd;
 }
 
+/*
+ * Read a single MSR from an open file descriptor
+ */
 static int __attribute__((warn_unused_result))
 read_msr(int fd, off_t offset, unsigned long long *msr)
 {
@@ -301,6 +348,10 @@ read_msr(int fd, off_t offset, unsigned long long *msr)
        return 0;
 }
 
+/*
+ * Open a MSR device for reading, read the value asked for and close it.
+ * This call will not affect the scheduling affinity of this thread.
+ */
 static int __attribute__((warn_unused_result))
 get_msr(int cpu, off_t offset, unsigned long long *msr)
 {
@@ -727,6 +778,7 @@ for_all_proc_cpus(int (func)(int))
        retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
        if (retval != 0) {
                ERROR("Failed to parse /proc/stat");
+               fclose(fp);
                return -ERR_CANT_READ_PROC_STAT;
        }
 
@@ -971,7 +1023,7 @@ check_super_user()
  * This is usually equal to tjMax.
  *
  * Older processors do not have this MSR, so there we guess,
- * but also allow cmdline over-ride with -T.
+ * but also allow conficuration over-ride with "TCCActivationTemp".
  *
  * Several MSR temperature values are in units of degrees-C
  * below this value, including the Digital Thermal Sensor (DTS),
@@ -1153,28 +1205,28 @@ probe_cpu()
                case 0x3A: /* IVB */
                case 0x3E: /* IVB Xeon */
                        do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
-                       do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+                       do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
                        break;
                /* Haswell Bridge */
                case 0x3C: /* HSW */
                case 0x3F: /* HSW */
                case 0x46: /* HSW */
                        do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
-                       do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+                       do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
                        break;
                case 0x45: /* HSW */
                        do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
-                       do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10);
+                       do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10);
                        break;
                /* Broadwel */
                case 0x4F: /* BDW */
                case 0x56: /* BDX-DE */
                        do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
-                       do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+                       do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
                        break;
                case 0x3D: /* BDW */
                        do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
-                       do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10);
+                       do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10);
                        break;
                default:
                        ERROR("Unsupported CPU");