- do_nehalem_platform_info = genuine_intel;
- do_nhm_cstates = genuine_intel; /* all Intel w/ non-stop TSC have NHM counters */
- do_smi = do_nhm_cstates;
- do_snb_cstates = is_snb(family, model);
- do_c8_c9_c10 = has_c8_c9_c10(family, model);
- do_slm_cstates = is_slm(family, model);
+ /*
+ * Enable or disable C states depending on the model and family
+ */
+ if (family == 6) {
+ switch (model) {
+ /* Atom (partial) */
+ case 0x27:
+ do_core_cstate = 0;
+ do_pkg_cstate = (1 << 2) | (1 << 4) | (1 << 6);
+ break;
+ /* Silvermont */
+ case 0x37: /* BYT */
+ case 0x4A:
+ case 0x4D: /* AVN */
+ case 0x5A:
+ case 0x5D:
+ do_core_cstate = (1 << 1) | (1 << 6);
+ do_pkg_cstate = (1 << 6);
+ break;
+ /* Nehalem */
+ case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
+ case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
+ case 0x1F: /* Core i7 and i5 Processor - Nehalem */
+ case 0x2E: /* Nehalem-EX Xeon - Beckton */
+ do_core_cstate = (1 << 3) | (1 << 6);
+ do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ /* Westmere */
+ case 0x25: /* Westmere Client - Clarkdale, Arrandale */
+ case 0x2C: /* Westmere EP - Gulftown */
+ case 0x2F: /* Westmere-EX Xeon - Eagleton */
+ do_core_cstate = (1 << 3) | (1 << 6);
+ do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ /* Sandy Bridge */
+ case 0x2A: /* SNB */
+ case 0x2D: /* SNB Xeon */
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 2) | (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ /* Ivy Bridge */
+ case 0x3A: /* IVB */
+ case 0x3E: /* IVB Xeon */
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ /* Haswell Bridge */
+ case 0x3C: /* HSW */
+ case 0x3F: /* HSW */
+ case 0x46: /* HSW */
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ case 0x45: /* HSW */
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10);
+ break;
+ /* Broadwel */
+ case 0x4F: /* BDW */
+ case 0x56: /* BDX-DE */
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ break;
+ case 0x3D: /* BDW */
+ do_core_cstate = (1 << 3) | (1 << 6) | (1 << 7);
+ do_pkg_cstate = (1 << 3) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10);
+ break;
+ default:
+ ERROR("Unsupported CPU");
+ }
+ switch (model) {
+ case 0x2A:
+ case 0x3A:
+ case 0x3C:
+ case 0x45:
+ case 0x46:
+ do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_PKG_POWER_INFO | RAPL_GFX;
+ break;
+ case 0x3F:
+ do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM | RAPL_DRAM_PERF_STATUS;
+ break;
+ case 0x2D:
+ case 0x3E:
+ do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_PKG_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM | RAPL_DRAM_PERF_STATUS;
+ break;
+ case 0x37:
+ case 0x4D:
+ do_rapl = RAPL_PKG | RAPL_CORES;
+ break;
+ default:
+ do_rapl = 0;
+ }
+ } else {
+ ERROR("Unsupported CPU");
+ return -UNSUPPORTED_CPU;
+ }